New Components for Future Computer Memories

The European TRAMS (terascale reliable adaptive memory systems) consortium funded under FP7 investigates the impact of statistical NanoCMOS variability on terascale embedded static random-access memories (SRAMs) based on sub-16 nm technology generation using conventional and novel complementary metal-oxide semiconductor (CMOS) devices.

The statistical variability introduced by the discreteness of charge and matter has become a major obstacle to scaling and integration. Its impact on embedded memories is particularly dramatic, as its slows down supply voltage scaling (particularly for SRAMs) and threatens the continuation of area scaling that helps drive integration targets for systems on chip.

Concerns regarding the area of SRAM cells and power supply scaling are major drivers behind the revolutionary introduction of FinFET devices. TRAMS is striving to understand the implications of FinFET technology for the continuation of CMOS scaling as projected by Moore's law.

This year, TRAMS completed an important milestone by analysing in minute detail the statistical variability in a 10 nm-channel length FinFET on silicon-on-insulator (SOI) substrate using advanced statistical technology computer-aided design (TCAD) simulation. The FinFETs are carefully designed to meet the requirements of the International Technology Roadmap for Semiconductors (ITRS) for 11-nm CMOS technology generation. The simulations have been carried out using unique simulation technology that takes into account the major known sources of statistical variability and reliability, including random discrete dopants, the gate and the fin line edge roughness, the metal gate variability and bias temperature instability effects (e.g., NBTI/PBTI).

The results of the physical simulations have been captured in accurate statistical compact models by the TRAMS partners. These models are being used to evaluate the impact of statistical FinFET variability on the design of 11-nm embedded memories and to develop circuit and system countermeasures that will make future embedded memories resilient to statistical variability and reliability.